A semiconductor device having double-layered wiring namely, a device having lower and upper wiring layers will be described as an example. This semiconductor device is manufactured as follows.
First, the lower wiring layer is provided on a semiconductor substrate. Next, an insulating layer is provided on both the lower wiring layer and the substrate. Finally, the upper wiring layer is provided on the insulating layer. Before this final step, the surface of the insulating layer must be flattened. Typically, a side wall method is used for flattening the surface of the insulating layer.
The case where the side wall method is used to the manufacture of a bipolar transistor will now be described, with reference to FIG. 1A to FIG. 1D.
Referring to FIG. 1A, N-type semiconductor substrate 11 is used as a collector region. In the surface region of substrate 11, P-type base region 12 is formed by impurity diffusion. Thereafter, N-type emitter region 13 and P.sup.+ region 14 are formed in the surface region of base region 12. Next, SiO.sub.2 layer 15 is formed on the surface of region 11, in such a manner that regions 12, 13, and 14 are all covered by SiO.sub.2 layer 15. Contact holes are formed in those portions of SiO.sub.2 layer 15 which correspond to the locations of regions 13 and 14. After this, an Al layer is formed on the entire surface of SiO.sub.2 layer 15. By patterning this Al layer, emitter and base electrodes 16 and 17 are formed. Electrodes 16 and 17 are in contact with regions 13 and 14, respectively, and constitute a lower wiring layer. Next, CVD-SiO.sub.2 layer 18 is formed on the entire surface of SiO.sub.2 layer 15. CVD-SiO.sub.2 layer 18 is removed by reactive ion etching, but this etching is performed such that part 18a of CVD-SiO.sub.2 18 remains on the side walls of electrodes 16 and 17, as is shown in FIG. 1B. After this, CVD-SiO.sub.2 layer 19 is deposited over layer 15. After contact holes 21 and 22 are formed in layer 19, an Al layer is deposited over layer 19. By patterning this Al layer, electrodes 23 and 24, which constitute an upper wiring layer, are formed as shown in FIG. 1C. Thereafter, protecting film 25 is formed both on CVD-SiO.sub.2 layer 19 and on electrodes 23 and 24. Contact holes 26 and 27 are formed in those portions of protecting film 25 which correspond to the locations of electrodes 23 and 24, thereby these exposing these electrodes. Next, bonding wires 28 and 29 are bonded to the upper surface of electrodes 23 and 24, thereby enabling the base and emitter to be led to an external circuit. Terminal 30, used for leading the collector to an external circuit, is connected to the surface opposite to the main surface of substrate 11.
In the prior art semiconductor device mentioned above, the shape of CVD-SiO.sub.2 layer 18a remaining on the side walls of electrodes 16 and 17 is apt to vary greatly, depending on circumstances. Accordingly, the foundation on which electrodes 23 and 24 are formed is apt to vary in shape greatly, resulting in deterioration in the quality of the Al film. If this happens, migration is likely to occur in electrodes 23 and 24, so that the reliability of the contact portions between the electrodes of the upper wiring layer and those of the lower wiring layer will be degraded.
In the prior art semiconductor device, electrodes 16 and 17 of the lower wiring layer constituting the foundation are formed of Al, which is not very hard. Therefore, CVD-SiO.sub.2 film 19, which serves as an interlayer insulating film, is likely to crack if the wires are bonded directly to electrodes 23 and 24.